Wednesday, March 19, 2008
Intel discussed upcoming leading edge microprocessors and technologies. Nehalem is scalable with future versions having anywhere from 2 to 8 cores, with Simultaneous Multi-threading, resulting in 4 to 16 thread capability, 8 MB level-3 cache, 731 million transistors, Quickpath interconnects (up to 25.6GB per second), integrated memory controller and optional integrated graphics. The Larrabee architecture includes a high-performance, wide SIMD vector processing unit (VPU) along with a new set of vector instructions including integer and floating point arithmetic, vector memory operations and conditional instructions. In addition, Larrabee includes a major new hardware coherent cache design enabling the many-core architecture. Intel AVX when used by software programmers, will increase performance in floating point, media, and processor intensive software. The instructions will be implemented in the microarchitecture codenamed "Sandy Bridge" in the 2010 timeframe.
Posted by GayanX86 at 9:27 AM